The present invention relates to high performance, high frequency memory controllers and, more specifically, to efficiently decoding address information therein.
Typical prior art computer systems may require several system clock cycles to perform all of the necessary decode operations for a main memory (usually DRAM) access cycle.
One reason for the undesirable delay in performing a DRAM cycle is that common configurable memory modules such as SIMMs, DIMMs and the like may be of different sizes, requiring a different number of address bits and logic for processing the different number of address bits. This problem may exist whether the memory configuration is original or contains upgrades, and tends to be exacerbated in upgraded memory configurations. Another reason for undesirable decode delays is the requisite processing time of logic that supports a number of memory banks that is other than a power of two (2). Each of these addressing conditions increases the amount of time required for decoding address information for a DRAM cycle.
Accordingly, it is an object of the present invention to more efficiently decode address information (i.e., physical memory location) so as to require fewer clock cycles to complete a memory access cycle.
It is another object of the present invention to provide a memory controller that pre-decodes address information for a memory access cycle.
It is another object of the present invention to provide a memory controller that pre-decodes bank select information for a memory access cycle.
It is also an object of the present invention to provide a memory controller that pre-decodes bank select information for efficient paging.
These and related objects of the present invention are achieved by use of a bank information pre-decode apparatus as described and claimed herein. In one embodiment of the present invention the bank information pre-decode apparatus includes an address bus; a memory access request queue coupled to said address bus; a multi-bank memory and associated memory control logic coupled to said request queue; and decode logic coupled between said address bus and said memory that decodes bank information from a signal from said address bus; wherein said bank information is propagated to said memory control logic to facilitate a rapid memory access cycle. The bank information is preferably a bank select signal.
In further embodiments, the bank information is propagated through said request queue to said memory (said bank information being propagated from said decode logic to a corresponding request in said request queue), and said decode logic comprises comparator logic that compares the signal received from said address bus with a plurality of values that indicate address boundaries of banks in a multi-bank memory. The bank information may includes a plurality of bits, each bit indicative of one of the banks in said multi-bank memory. Memory paging logic may also be provided that receives said bank information at least when the request corresponding to that bank information is popped off said queue to said control logic and begins memory paging based on that bank information.
The attainment of the foregoing and related advantages and features of the invention should be more readily apparent to those skilled in the art, after review of the following more detailed description of the invention taken together with the drawings.